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Cyrix 6x86 MX Architechure
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Shortly after the release of the Pentium 2, Cyrix released the 6x86MX processor. Unlike AMD, Cyrix aimed their processor right at the Pentium 2. Of the sixth generation processors, the 6x86MX is the only non-RISC processor on my site. Also, the 6x86MX isn't operating at the same Mhz as the processors from AMD and Intel. They use a performance rating, which rates the speed of their processors relative to those from Intel. The 6x86MX-PR233 has a performance rating of 233 MHz but actually it's only operating at 188 MHz. The 6x86MX-PR233 uses a 75 MHz bus speed with a clock multiplier of 2.5. (The PR200 is actually a 166 MHz processor with a 66 MHz bus and the PR166 is actually a 150 MHz processor with a 60 MHz bus) Well, all this makes it sound like the 6x86MX won't perform as well as the Pentium 2 when it comes to real-world performance, lets check out the architecture and see if they have some tricks up their sleeve.... The Cyrix 6x86MX contains a bus interface unit, cache unit, integer unit, floating point unit, and memory management unit.
Bus Interface Unit
Cache Unit
Memory Management Unit
Branch target buffer
The integer unit contains two seven-stage integer pipelines. (X and Y) Certain instructions are processed in the X pipeline that aren't done in the Y. The 6x86MX's integer unit supports these architectural features: Data Bypassing: Wondering what this is, eh? Well I'll try to explain it in as few big words as possible. :) Basically, when data from an instruction is written to memory and the next instruction reads that same data from that memory, a memory read cycle will occur. (The second instruction needs the original data, not the newly written on stuff) With data bypassing, the original data is kept and passed on to the second instruction. The above scenario is called a read-after-write dependency. Data Forwarding: Data forwarding is another technique used to solve read-after-write dependencies. It can resolve the issue in either of two ways (depending on the situation) operand forwarding, or result forwarding. Operand forwarding is similar to the previous example because the original data is needed by the second instruction, with operand forwarding, the original data is available to both instructions. Result forwarding occurs when the results of the first instruction are needed by the second instruction, the 6x86MX processes the instruction and stores the results for both instructions. Out-of-order execution: Again, out-of-order execution occurs when one instruction is processed faster than the instruction in the other pipeline. If this happens, the instructions can complete out-of-order. Register Renaming: The 6x86MX contains 32 physical general purpose registers. These registers can be "renamed" to store instruction results. Speculative Execution: Lets say a branch instruction pops up, (branch instructions require the processor to go to a different part of the program) well if this occurs a pipeline stall happens. (The pipeline stalls because the processor is looking for the location of the branch instruction instead of crunching the code) Enter speculative execution, with speculative execution the pipeline no longer stalls because instructions can be executed while the branch instructions' address is being determined. The 6x86MX CPU supports up to 4 levels of speculation. (i.e. can perform speculative execution as long as there are no more than 4 unresolved branch instructions) Once the branch instruction is complete, the level of speculation is decreased, if the branch's address is mispredicted, the 6x86MX determines the correct address and then is able to return to it's original state in a single clock cycle.
Floating Point Unit Sorry the image looks so bad guys, nothing I can do about that. Well, I was hoping this image would help explain the stages the 6x86MX goes through when processing instructions. 1.Fetch stage, fetches 16 bytes of code from the cache unit in a single clock cycle. During the fetch stage, the code is checked for any branch instructions. 2.Instructions are sent to the X or Y pipeline in the integer unit for execution. (Depending on what type of instruction it is, the instruction could also end up in the branch target buffer or the floating point unit) I don't know if you can read it or not, but contained in the CPU core (in the image) is the FPU, branch target buffer, and integer unit. 3.After leaving the CPU core the instruction is sent to the memory management unit where it is given a physical address to be used by the unified cache and bus interface. (In some cases, it can also go straight to the cache unit) 4.The instruction is sent to the cache unit, and then sent to the bus interface unit 5.The instruction can now be sent anywhere on the system motherboard
Conclusion
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